Semiconductor device manufacturing method and semiconductor integrated circuit device

ABSTRACT

A semiconductor device manufacturing method includes forming a first insulating film on a semiconductor substrate, forming a first conductor film on the first insulating film, forming a second insulating film on the first conductor film, forming a first line-and-space pattern by etching the second insulating film and the first conductor film, forming a etched region etched into a second line-and-space pattern perpendicular to the first line-and-space pattern by etching the second insulating film, the first conductor film, the first insulating film, and the semiconductor substrate, burying a third insulating film in the etched region, removing the second insulating film, forming a fourth insulating film on the first conductor film and the third insulating film, forming a second conductor film on the fourth insulating film, and forming a third line-and-space pattern parallel to the first line-and-space pattern by etching the second conductor film.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromprior Japanese Patent Application No. 2006-127037, filed Apr. 28, 2006,the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device manufacturingmethod and semiconductor integrated circuit device and, moreparticularly, to a method of manufacturing a nonvolatile semiconductormemory device having stacked gate memory cells.

2. Description of the Related Art

As an example of the related art, manufacturing steps from the formationof element isolation regions (shallow trench isolations) to theformation of gate lines (word lines) of a memory cell array in a NANDnonvolatile semiconductor memory will be explained below.

FIG. 43 is a flowchart showing the well-known sequence from shallowtrench isolation formation to word line formation. This sequence shownin FIG. 43 is illustrated in, e.g., FIGS. 2( a) to 2(d) of S. Aritome etal., “A 0.67-μm² SELF-ALIGNED SHALLOW TRENCH ISOLATION CELL (SA-STICELL) FOR 3V-only 256-Mbit NAND EEPROMs,”, IEDM, pp. 61-64, 1994.

FIG. 44 is a plan view of the memory cell array formed following theprocedure shown in FIG. 43. FIG. 45A is a sectional view taken along aline 45-45 in FIG. 44.

First, as indicated by ST1 in FIG. 43, a tunnel insulating film 5 isformed on a semiconductor substrate 4, and a floating gate (FG)conductor film 6 is deposited on the tunnel insulating film 5.

Then, as indicated by ST2, an element region (AA) mask pattern is formedon the floating gate conductor film 6, and used as an etching mask todry-etch the floating gate conductor film 6 and semiconductor substrate4, thereby forming shallow trenches in the semiconductor substrate 4 andseparating the floating gate conductor film 6 in the bit line directionat the same time.

As indicated by ST3, an insulator (STI) 9 is buried in the shallowtrenches formed in the semiconductor substrate 4. Subsequently, aninterpoly insulating film 10 that insulates floating gates from wordlines is formed on the floating gate conductor film 6 and insulator 9. Aword line conductor film 11 is deposited on the interpoly insulatingfilm 10.

As indicated by ST4, a word line mask pattern 12 is formed on the wordline conductor film 11, and used as an etching mask to dry-etch the wordline conductor film 11, interpoly insulating film 10, and floating gateconductor film 6, thereby forming word lines WL and separating thefloating gate conductor film 6 in the word line direction at the sametime. FIGS. 45B and 45C illustrate this etching process. Note thatsimilar to FIG. 45A, FIGS. 45B and 45C are sectional views taken alongthe line 45-45 in FIG. 44.

In these sectional views shown in FIGS. 45B and 45C, however, thefloating gates 6 and insulating films 9 are actually tapered as shown inFIGS. 46A and 46B for the following reason. That is, due to thecharacteristics of dry etching for forming the shallow trenches in ST3,this etching progresses while depositing deposition films made of theetching product on the sidewalls. As shown in FIG. 46B, this taperforms, on the semiconductor substrate 4, portions hidden behind theinsulating films 9 and interpoly insulating films 10. The floating gates6 sometimes remain in these hidden portions without being etched. Ifthese residues form, adjacent floating gates 6 shortcircuit. FIG. 47A isa plan view showing an ideal pattern (Design) of the floating gates (FG)6 on the memory cell array. FIG. 47B is a plan view showing a pattern(Actual) of the floating gates (FG) 6 when the residues form.

If the residues form, as shown in FIG. 47B, the floating gates 6 do notform patterns independent of each other, but insufficiently separatefrom each other in the word line direction. Consequently, adjacentfloating gates 6 connect to each other in the form of a chain along thebit line direction.

BRIEF SUMMARY OF THE INVENTION

A semiconductor device manufacturing method according to the firstaspect of the present invention comprises forming a first insulatingfilm on a semiconductor substrate, forming a first conductor film on thefirst insulating film, forming a second insulating film on the firstconductor film, forming a first line-and-space pattern by etching thesecond insulating film and the first conductor film, forming a etchedregion etched into a second line-and-space pattern perpendicular to thefirst line-and-space pattern by etching the second insulating film, thefirst conductor film, the first insulating film, and the semiconductorsubstrate, burying a third insulating film in the etched region,removing the second insulating film, forming a fourth insulating film onthe first conductor film and the third insulating film, forming a secondconductor film on the fourth insulating film, and forming a thirdline-and-space pattern parallel to the first line-and-space pattern byetching the second conductor film.

A semiconductor device manufacturing method according to the secondaspect of the present invention comprises forming a first insulatingfilm on a semiconductor substrate, forming a first conductor film on thefirst insulating film, forming a second insulating film on the firstconductor film, forming a first line-and-space pattern by etching thesecond insulating film and the first conductor film, forming a etchedregion etched into a second line-and-space pattern perpendicular to thefirst line-and-space pattern by etching the second insulating film, thefirst conductor film, the first insulating film, and the semiconductorsubstrate, burying a third insulating film in the etched region, etchingthe third insulating film to a middle of the second insulating film,forming a film on the etched region, implanting an impurity into thefilm parallel to the first line-and-space pattern and obliquely to thesemiconductor substrate to form a first portion where the impurity isnot implanted into the film and a second portion where the impurity isimplanted into the film, etching the first portion, etching the thirdinsulating film to a middle of a film thickness of the first conductorfilm by using the second portion and the second insulating film asmasks, removing the second portion and the second insulating film,forming a fourth insulating film on the first conductor film and thethird insulating film, forming a second conductor film on the fourthinsulating film, and partially removing the second conductor film toform a buried interconnection formed of the second conductor film.

A semiconductor integrated circuit device according to the third aspectof the present invention comprises a semiconductor substrate having anelement isolation region extending in a first direction, and an elementregion defined by the element isolation region, a gate insulating filmformed on the element region, a charge storage layer formed on the gateinsulating film, and having a first side surface and a second sidesurface along the first direction and a third side surface and a fourthside surface along a second direction perpendicular to the firstdirection, the first side surface being in contact with the elementisolation region, a first insulating film formed above the elementregion, and in contact with the third side surface of the charge storagelayer, a second insulating film formed above the element region, and incontact with the fourth side surface of the charge storage layer, aninter-gate insulating film formed on the first insulating film, thesecond insulating film, the charge storage layer, and the elementisolation region, and a control gate formed on the inter-gate insulatingfilm, opposing the charge storage layer via the inter-gate insulatingfilm, and extending in the second direction.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is a flowchart showing an example of the sequence of asemiconductor device manufacturing method according to the firstembodiment of the present invention;

FIG. 2 is a plan view showing an example of a semiconductor devicemanufacturing method according to the second embodiment of the presentinvention in the order of main manufacturing steps;

FIG. 3A is a sectional view taken along a line A-A in FIG. 2;

FIG. 3B is a sectional view taken along a line B-B in FIG. 2;

FIG. 4 is a plan view showing the example of the semiconductor devicemanufacturing method according to the second embodiment of the presentinvention in the order of main manufacturing steps;

FIG. 5A is a sectional view taken along a line A-A in FIG. 4;

FIG. 5B is a sectional view taken along a line B-B in FIG. 4;

FIG. 6 is a plan view showing the example of the semiconductor devicemanufacturing method according to the second embodiment of the presentinvention in the order of main manufacturing steps;

FIG. 7A is a sectional view taken along a line A-A in FIG. 6;

FIG. 7B is a sectional view taken along a line B-B in FIG. 6;

FIG. 8 is a plan view showing the example of the semiconductor devicemanufacturing method according to the second embodiment of the presentinvention in the order of main manufacturing steps;

FIG. 9A is a sectional view taken along a line A-A in FIG. 8;

FIG. 9B is a sectional view taken along a line B-B in FIG. 8;

FIG. 10 is a plan view showing the example of the semiconductor devicemanufacturing method according to the second embodiment of the presentinvention in the order of main manufacturing steps;

FIG. 11A is a sectional view taken along a line A-A in FIG. 10;

FIG. 11B is a sectional view taken along a line B-B in FIG. 10;

FIG. 12 is a plan view showing the example of the semiconductor devicemanufacturing method according to the second embodiment of the presentinvention in the order of main manufacturing steps;

FIG. 13A is a sectional view taken along a line A-A in FIG. 12;

FIG. 13B is a sectional view taken along a line B-B in FIG. 12;

FIG. 14 is a plan view showing the example of the semiconductor devicemanufacturing method according to the second embodiment of the presentinvention in the order of main manufacturing steps;

FIG. 15A is a sectional view taken along a line A-A in FIG. 14;

FIG. 15B is a sectional view taken along a line B-B in FIG. 14;

FIG. 16 is a plan view showing the example of the semiconductor devicemanufacturing method according to the second embodiment of the presentinvention in the order of main manufacturing steps;

FIG. 17A is a sectional view taken along a line A-A in FIG. 16;

FIG. 17B is a sectional view taken along a line B-B in FIG. 16;

FIG. 18 is a plan view showing the example of the semiconductor devicemanufacturing method according to the second embodiment of the presentinvention in the order of main manufacturing steps;

FIG. 19A is a sectional view taken along a line A-A in FIG. 18;

FIG. 19B is a sectional view taken along a line B-B in FIG. 18;

FIG. 20 is a plan view showing the example of the semiconductor devicemanufacturing method according to the second embodiment of the presentinvention in the order of main manufacturing steps;

FIG. 21A is a sectional view taken along a line A-A in FIG. 20;

FIG. 21B is a sectional view taken along a line B-B in FIG. 20;

FIGS. 22A and 22B are sectional views showing an example of asemiconductor device manufacturing method according to the thirdembodiment of the present invention in the order of main manufacturingsteps, in which FIG. 22A is a sectional view corresponding to the lineA-A in FIG. 12, and FIG. 22B is a sectional view corresponding to theline B-B in FIG. 12;

FIGS. 23A and 23B are sectional views showing the example of thesemiconductor device manufacturing method according to the thirdembodiment of the present invention in the order of main manufacturingsteps, in which FIG. 23A is a sectional view corresponding to the lineA-A in FIG. 14, and FIG. 23B is a sectional view corresponding to theline B-B in FIG. 14;

FIGS. 24A and 24B are sectional views showing the example of thesemiconductor device manufacturing method according to the thirdembodiment of the present invention in the order of main manufacturingsteps, in which FIG. 24A is a sectional view corresponding to the lineA-A in FIG. 16, and FIG. 24B is a sectional view corresponding to theline B-B in FIG. 16;

FIGS. 25A and 25B are sectional views showing the example of thesemiconductor device manufacturing method according to the thirdembodiment of the present invention in the order of main manufacturingsteps, in which FIG. 25A is a sectional view corresponding to the lineA-A in FIG. 18, and FIG. 25B is a sectional view corresponding to theline B-B in FIG. 18;

FIGS. 26A and 26B are sectional views showing the example of thesemiconductor device manufacturing method according to the thirdembodiment of the present invention in the order of main manufacturingsteps, in which FIG. 26A is a sectional view corresponding to the lineA-A in FIG. 20, and FIG. 26B is a sectional view corresponding to theline B-B in FIG. 20;

FIG. 27 is a plan view showing an example of a semiconductor devicemanufacturing method according to the fourth embodiment of the presentinvention in the order of main manufacturing steps;

FIG. 28A is a sectional view taken along a line A-A in FIG. 27;

FIG. 28B is a sectional view taken along a line B-B in FIG. 27;

FIG. 29 is a plan view showing the example of the semiconductor devicemanufacturing method according to the fourth embodiment of the presentinvention in the order of main manufacturing steps;

FIG. 30A is a sectional view taken along a line A-A in FIG. 29;

FIG. 30B is a sectional view taken along a line B-B in FIG. 29;

FIG. 31 is a plan view showing the example of the semiconductor devicemanufacturing method according to the fourth embodiment of the presentinvention in the order of main manufacturing steps;

FIG. 32A is a sectional view taken along a line A-A in FIG. 31;

FIG. 32B is a sectional view taken along a line B-B in FIG. 31;

FIG. 33 is a plan view showing the example of the semiconductor devicemanufacturing method according to the fourth embodiment of the presentinvention in the order of main manufacturing steps;

FIG. 34A is a sectional view taken along a line A-A in FIG. 33;

FIG. 34B is a sectional view taken along a line B-B in FIG. 33;

FIG. 34C is a macrograph of a part of FIG. 34A;

FIG. 35 is a plan view showing the example of the semiconductor devicemanufacturing method according to the fourth embodiment of the presentinvention in the order of main manufacturing steps;

FIG. 36A is a sectional view taken along a line A-A in FIG. 35;

FIG. 36B is a sectional view taken along a line B-B in FIG. 35;

FIG. 37 is a plan view showing the example of the semiconductor devicemanufacturing method according to the fourth embodiment of the presentinvention in the order of main manufacturing steps;

FIG. 38A is a sectional view taken along a line A-A in FIG. 37;

FIG. 38B is a sectional view taken along a line B-B in FIG. 37;

FIG. 39 is a plan view showing the example of the semiconductor devicemanufacturing method according to the fourth embodiment of the presentinvention in the order of main manufacturing steps;

FIG. 40A is a sectional view taken along a line A-A in FIG. 39;

FIG. 40B is a sectional view taken along a line B-B in FIG. 39;

FIG. 41 is a plan view showing the example of the semiconductor devicemanufacturing method according to the fourth embodiment of the presentinvention in the order of main manufacturing steps;

FIG. 42A is a sectional view taken along a line A-A in FIG. 41;

FIG. 42B is a sectional view taken along a line B-B in FIG. 41;

FIG. 43 is a flowchart showing the well-known sequence from shallowtrench isolation formation to word line formation;

FIG. 44 is a plan view of a memory cell array formed following theprocedure shown in FIG. 43;

FIG. 45A is a sectional view taken along a line 45-45 in FIG. 44;

FIGS. 45B and 45C are sectional views showing the process of forming thesection taken along the line 45-45 in FIG. 44;

FIGS. 46A and 46B are sectional views showing the actual process offorming the sections shown in FIGS. 45B and 45C;

FIG. 47A is a plan view showing an ideal floating gate pattern;

FIG. 47B is a plan view showing a floating gate pattern when residuesform;

FIGS. 48 and 49 are sectional views showing an example of asemiconductor integrated circuit device according to the fifthembodiment of the present invention;

FIGS. 50 to 52 are perspective views showing the example of thesemiconductor integrated circuit device according to the fifthembodiment of the present invention;

FIGS. 53A to 53C are views for explaining the advantage obtained fromthe semiconductor integrated circuit device according to the fifthembodiment of the present invention;

FIGS. 54A to 54C are views showing a semiconductor integrated circuitdevice according to a reference example;

FIGS. 55 and 56 are sectional views showing an example of asemiconductor integrated circuit device according to the sixthembodiment of the present invention;

FIGS. 57 to 59 are perspective views showing the example of thesemiconductor integrated circuit device according to the sixthembodiment of the present invention;

FIGS. 60 and 61 are sectional views showing an example of asemiconductor integrated circuit device according to the seventhembodiment of the present invention;

FIGS. 62 to 64 are perspective views showing the example of thesemiconductor integrated circuit device according to the seventhembodiment of the present invention;

FIGS. 65A to 65C are views for explaining the advantage obtained fromthe semiconductor integrated circuit device according to the seventhembodiment of the present invention;

FIGS. 66A to 66C are views showing a semiconductor integrated circuitdevice according to a reference example;

FIG. 67 is a circuit diagram showing an application example of thesemiconductor integrated circuit device according to the seventhembodiment of the present invention;

FIGS. 68 and 69 are sectional views showing an example of asemiconductor integrated circuit device according to the eighthembodiment of the present invention;

FIGS. 70 to 72 are perspective views showing the example of thesemiconductor integrated circuit device according to the eighthembodiment of the present invention;

FIGS. 73A and 73B are views for explaining advantage 1 obtained from thesemiconductor integrated circuit device according to the eighthembodiment of the present invention;

FIGS. 74A and 74B are views showing a semiconductor integrated circuitdevice according to a reference example;

FIG. 75 is a sectional view showing an example of a semiconductorintegrated circuit device from which advantage 1 is obtained better;

FIG. 76 is a view for explaining advantage 2 obtained from thesemiconductor integrated circuit device according to the eighthembodiment of the present invention;

FIG. 77 is a view showing a semiconductor integrated circuit deviceaccording to a reference example;

FIGS. 78A and 78B are circuit diagrams for explaining the proximityeffect;

FIG. 79A is a graph showing a threshold voltage distribution beforesuffering the proximity effect;

FIG. 79B is a graph showing a threshold voltage distribution aftersuffering the proximity effect;

FIG. 80A is a graph showing a threshold voltage distribution beforesuffering the proximity effect;

FIG. 80B is a graph showing a threshold voltage distribution aftersuffering the proximity effect;

FIG. 81A is a graph showing a threshold voltage distribution beforesuffering the proximity effect;

FIG. 81B is a graph showing a threshold voltage distribution aftersuffering the proximity effect;

FIG. 82 is a view for explaining advantage 3 obtained from thesemiconductor integrated circuit device according to the eighthembodiment of the present invention;

FIG. 83 is a view showing a semiconductor integrated circuit deviceaccording to a reference example;

FIG. 84 is a sectional view taken along the bit line direction, whichshows one block of a NAND flash memory to which an embodiment of thepresent invention is applied;

FIG. 85 is an operation timing chart showing a self-boost write method;

FIG. 86 is a sectional view showing state I in FIG. 85; and

FIG. 87 is a sectional view showing state II in FIG. 85.

DETAILED DESCRIPTION OF THE INVENTION

Several embodiments of the present invention will be explained belowwith reference to the accompanying drawing. Note that the same referencenumerals denote the same parts in the drawing.

First Embodiment

The first embodiment is the basis of the embodiments of the presentinvention. The first embodiment shows a procedure capable of preventinga shortcircuit of adjacent conductor patterns, e.g., a shortcircuit ofadjacent floating gates, and shows an example of the sequence of theprocedure.

The point of the first embodiment is that floating gates of memory cellsof a stacked gate NAND flash memory are first separated along the wordline direction, and then separated along the bit line direction byforming shallow trenches.

As described above, the first embodiment can prevent insufficientseparation of the floating gates in the word line direction byseparating the floating gates along the word line direction beforeforming shallow trenches that cause taper. As a consequence, a stackedgate NAND flash memory can be manufactured with high yield.

FIG. 1 is a flowchart showing an example of the sequence of asemiconductor device manufacturing method according to the firstembodiment of the present invention.

First, as indicated by ST1 in FIG. 1, a tunnel insulating film is formedon a semiconductor substrate, and a floating gate (FG) conductor film isdeposited on the tunnel insulating film.

Then, as indicated by ST2, a separation mask pattern for separatingfloating gates along the word line direction is formed on the floatinggate conductor film. This separation mask pattern is used as an etchingmask to etch the floating gate conductor film, thereby separating italong the word line direction.

As indicated by ST3, after the separation mask pattern is removed, anelement region (AA) mask pattern is formed on the semiconductorsubstrate and floating gate conductor films. This element region maskpattern is used as an etching mask to etch the floating gate conductorfilms and semiconductor substrate, thereby forming shallow trenches inthe semiconductor substrate and separating the floating gate conductorfilms along the bit line direction at the same time.

Subsequently, as indicated by ST4, an insulator is buried in the shallowtrenches formed in the semiconductor substrate. An interpoly insulatingfilm for insulating floating gates from word lines is formed on thesemiconductor substrate, floating gate conductor films, and insulator. Aword line conductor film is then deposited on the interpoly insulatingfilm.

As indicated by ST5, a word line mask pattern is formed on the word lineconductor film. This word line mask pattern is used as an etching maskto dry-etch the word line conductor film and interpoly insulating film,thereby forming word lines WL.

As described above, the first embodiment separates the floating gatesalong the word line direction before forming the shallow trenches thatcause taper. That is, the floating gates are separated along the wordline direction before the insulator buried in the shallow trenches istapered. Therefore, no floating gates remain in hidden portions formedby the taper. This prevents insufficient separation of the floatinggates in the word line direction. As a consequence, a stacked gate NANDflash memory can be manufactured with high yield.

Second Embodiment

The second embodiment is the first example when the first embodiment isapplied to actual manufacturing steps.

FIGS. 2, 4, 6, 8, 10, 12, 14, 16, 18, and 20 are plan views showing anexample of a semiconductor device manufacturing method according to thesecond embodiment of the present invention in the order of mainmanufacturing steps. FIGS. 3A, 3B, 5A, 5B, 7A, 7B, 9A, 9B, 11A, 11B,13A, 13B, 15A, 15B, 17A, 17B, 19A, 19B, 21A, and 21B are sectional viewsshowing the example of the semiconductor device manufacturing methodaccording to the second embodiment of the present invention in the orderof main manufacturing steps.

First, as shown in FIGS. 2, 3A, and 3B, a tunnel insulating film 5 isformed on a silicon substrate 4. An example of the formation method isto thermally oxidize the silicon substrate 4 by a thickness of about 8nm. Then, a conductor film 6 for forming floating gates is formed on thetunnel insulating film 5. An example of the conductor film 6 is aphosphorus-doped polysilicon film into which phosphorus is doped. Anexample of the formation method is to deposit phosphorus-dopedpolysilicon about 140 nm thick on the tunnel insulating film 5 by usingLP-CVD (Low Pressure CVD). Subsequently, an insulating film (CAP) 7serving as a cap layer is formed on the phosphorus-doped polysiliconfilm 6. An example of the insulating film 7 is a silicon nitride film.An example of the formation method is to deposit silicon nitride about70 nm thick on the phosphorus-doped polysilicon film 6 by using LP-CVD.The silicon nitride film 7 is then coated with a photoresist PR to forma photoresist film. This photoresist film is patterned by usinglithography, thereby forming separation mask patterns 8 for separatingfloating gates along the word line direction.

As shown in FIGS. 4, 5A, and 5B, the separation mask patterns 8 are usedas etching masks to dry-etch the silicon nitride film 7 andphosphorus-doped polysilicon film 6. Then, the separation mask patterns8 are removed by ashing.

As shown in FIGS. 6, 7A, and 7B, an insulator (II) 14 is deposited onthe silicon nitride films 7 and tunnel insulating film 5 (or the siliconsubstrate 4). An example of the insulator 14 is a silicon oxide film. Anexample of the formation method is to deposit, on the silicon nitridefilms 7 and tunnel insulating film 5 (or the silicon substrate 4),silicon oxide by a thickness with which the silicon oxide fills thespaces between the phosphorus-doped polysilicon films 6, by using P-CVD(Plasma CVD). The silicon nitride films 7 are used as polishing stoppersto perform chemical-mechanical polishing (CMP) on the silicon oxidefilms 14, thereby burying the silicon oxide films 14 in the spacesbetween the phosphorus-doped polysilicon films 6.

As shown in FIGS. 8, 9A, and 9B, the silicon nitride films 7 and siliconoxide films 14 are coated with a photoresist PR to form a photoresistfilm. This photoresist film is patterned by using lithography, therebyforming element region (AA) mask patterns 8′.

As shown in FIGS. 10, 11A, and 11B, the element region mask patterns 8′are used as etching masks to etch the silicon nitride films 7, siliconoxide films 14, phosphorus-doped polysilicon films 6, and tunnelinsulating film 5, and further etch the silicon substrate 4, therebyforming shallow trenches ST in the silicon substrate 4. The elementregion mask patterns 8′ are then removed by ashing.

As shown in FIGS. 12, 13A, and 13B, an insulator 9 is deposited on thesilicon nitride films 7, silicon oxide films 14, and silicon substrate4. An example of the insulator 9 is a silicon oxide film. An example ofthe formation method is to deposit, on the silicon nitride films 7,silicon oxide films 14, and silicon substrate 4, silicon oxide by athickness with which the silicon oxide fills the shallow trenches ST, byusing P-CVD (Plasma CVD). Subsequently, the silicon nitride films 7 areused as polishing stoppers to perform chemical-mechanical polishing(CMP) on the silicon oxide film 9, thereby burying the silicon oxidefilm 9 in the shallow trenches ST. This forms element isolation regions(shallow trench isolations STI) that define element regions AA.

As shown in FIGS. 14, 15A, and 15B, the silicon nitride films 7 areremoved by wet etching by using the silicon oxide films 9 and 14 asetching masks, thereby exposing the upper surfaces of thephosphorus-doped polysilicon films 6.

As shown in FIGS. 16, 17A, and 17B, an interpoly insulator 10 isdeposited on the silicon oxide films 9 and 14 and phosphorus-dopedpolysilicon films 6. The interpoly insulator 10 insulates floating gatesfrom control gates (word lines). An example of the insulator 10 is asilicon oxide film. An example of the formation method is to depositsilicon oxide on the silicon oxide films 9 and 14 and phosphorus-dopedpolysilicon films 6 by using LP-CVD (Low Pressure CVD). An example ofthe interpoly insulator 10 can be the lamination structure having theinsulating films. Then, a conductor 11 is deposited on the silicon oxidefilm 10. The conductor 11 is the material of control gates (word lines).An example of the conductor 11 is a phosphorus-doped polysilicon film.An example of the formation method is to deposit phosphorus-dopedpolysilicon on the silicon oxide film 10 by using LP-CVD (Low PressureCVD). Subsequently, an insulator 12 is deposited on the phosphorus-dopedpolysilicon film 11. An example of the insulator 12 is a silicon nitridefilm. An example of the formation method is to deposit silicon nitrideon the phosphorus-doped polysilicon film 11 by using LP-CVD.

As shown in FIGS. 18, 19A, and 19B, the silicon nitride film 12 iscoated with a photoresist PR to form a photoresist film. Thisphotoresist film is then patterned by using lithography, thereby formingword line mask patterns 13.

As shown in FIGS. 20, 21A, and 21B, the word line mask patterns 13 areused as etching masks to dry-etch the silicon nitride film 12, andsuccessively dry-etch the phosphorus-doped polysilicon film 11. Afterthat, the word line mask patterns 13 are removed by ashing.

The above steps form a memory cell array of a stacked gate NAND flashmemory.

Similar to the first embodiment, the second embodiment also separatesthe phosphorus-doped polysilicon film 6 as the material of floatinggates along the word line direction (the step shown in FIGS. 4, 5A, and5B) before forming the shallow trenches ST that taper the silicon oxidefilms 9.

That is, the phosphorus-doped polysilicon film 6 is separated along theword line direction before the silicon oxide films 9 buried in theshallow trenches ST are tapered. Therefore, the phosphorus-dopedpolysilicon films 6 do not remain in hidden portions formed by thetaper. This prevents insufficient separation of the phosphorus-dopedpolysilicon films 6 in the word line direction. Consequently, the secondembodiment can also manufacture a stacked gate NAND flash memory withhigh yield, as in the first embodiment.

Third Embodiment

The third embodiment is the second example when the first embodiment isapplied to actual manufacturing steps.

The third embodiment particularly differs from the second embodiment inthat in the step shown in FIGS. 12, 13A, and 13B of the secondembodiment, the upper surfaces of the insulating films (STI) 9 buried inthe shallow trenches ST are lowered to the middle of the side surfacesof the conductor films 6 for forming floating gates, thereby exposingthe side surfaces of the conductor films 6.

FIGS. 22A and 22B to 26A and 26B are sectional views showing an exampleof a semiconductor device manufacturing method according to the thirdembodiment of the present invention in the order of main manufacturingsteps. Note that the sections shown in FIGS. 22A to 26A correspond tothe sections taken along the line A-A in FIGS. 12 to 20, and thesections shown in FIGS. 22B to 26B correspond to the sections takenalong the line B-B in FIGS. 12 to 20.

First, shallow trenches ST are formed in a silicon substrate 4 followingthe same procedure as explained in the second embodiment until the stepshown in FIGS. 10, 11A, and 11B.

Then, as shown in FIGS. 22A and 22B, an insulator 9 is deposited onsilicon nitride films 7, silicon oxide films 14, and the siliconsubstrate 4, and buried in the shallow trenches ST. An example of theinsulator 9 can be a silicon oxide film as in the first embodiment, andan example of the formation method can also be the same as in the firstembodiment. The silicon nitride films 7 are used as etching masks todry-etch the silicon nitride films 9. This embodiment dry-etches thesilicon oxide films 9 to the middle of the side surfaces of conductorfilms 6, in this embodiment, phosphorus-doped polysilicon films 6. Theupper surfaces of the silicon oxide films 9 are lowered to the middle ofthe side surfaces of the phosphorus-doped polysilicon films 6. Thisexposes the side surfaces of the phosphorus-doped polysilicon films 6.In this manner, element isolation regions (shallow trench isolationsSTI) that define element regions AA are formed in the silicon substrate4.

Note that in this embodiment, the insulating films 14 buried in thespaces between the phosphorus-doped polysilicon films 6 are the siliconoxide films 14, so the silicon oxide films 14 are also dry-etchedsimultaneously with the silicon oxide films 9. Therefore, asparticularly shown in FIG. 22B, the upper surfaces of the silicon oxidefilms 14 lower to the middle of the side surfaces of thephosphorus-doped polysilicon films 6 together with the upper surfaces ofthe silicon oxide films 9.

Subsequently, as shown in FIGS. 23A and 23B, the silicon oxide films 9and 14 are used as etching masks to wet-etch the silicon nitride films7, thereby removing the silicon nitride films 7.

As shown in FIGS. 24A and 24B, an interpoly insulator 10 is deposited onthe silicon oxide films 9 and 14 and phosphorus-doped polysilicon films6. An example of the interpoly insulator 10 can be the same as in thesecond embodiment, i.e., a silicon oxide film. An example of theformation method can also be the same as in the second embodiment. Then,a conductor 11 is deposited on the silicon oxide film 10. An example ofthe conductor 11 can be the same as in the second embodiment, i.e., aphosphorus-doped polysilicon film. An example of the formation methodcan also be the same as in the second embodiment. Subsequently, aninsulator 12 is deposited on the phosphorus-doped polysilicon film 11.An example of the insulator 12 is the same as in the second embodiment,i.e., a silicon nitride film. An example of the formation method is alsothe same as in the second embodiment.

As shown in FIGS. 25A and 25B, the silicon nitride film 12 is coatedwith a photoresist PR to form a photoresist film. This photoresist filmis then patterned by using lithography, thereby forming word line maskpatterns 13.

As shown in FIGS. 26A and 26B, the word line mask patterns 13 are usedas etching masks to dry-etch the silicon nitride film 12, andsuccessively dry-etch the phosphorus-doped polysilicon film 11. Afterthat, the word line mask patterns 13 are removed by ashing.

The above steps form a memory cell array of a stacked gate NAND flashmemory.

Similar to the first and second embodiments, the third embodiment alsoseparates the phosphorus-doped polysilicon film 6 as the material offloating gates along the word line direction before forming the shallowtrenches ST that taper the silicon oxide films 9. As in the first andsecond embodiments, therefore, the phosphorus-doped polysilicon films 6do not remain in hidden portions formed by the taper. This preventsinsufficient separation of the phosphorus-doped polysilicon films 6 inthe word line direction. Consequently, the third embodiment can alsomanufacture a stacked gate NAND flash memory with high yield, as in thefirst and second embodiments.

In addition, the third embodiment lowers the upper surfaces of theinsulating films (STI) 9 buried in the shallow trenches to the middle ofthe side surfaces of the conductor films 6 as floating gates, therebyexposing the side surfaces of the conductor films 6. When compared tothe second embodiment, therefore, as well shown in, e.g., FIG. 26A, theopposing area between the conductor films 6 and 11 can be increased.Accordingly, the capacitance between the floating gate and control gate(word line) can be made larger than that in the second embodiment.

Furthermore, as particularly shown in FIG. 26A, the floating gates 6 inthe word line direction sandwich the conductor film 11. This makes itpossible to decrease the capacitance between adjacent floating gatesalong the word line direction, compared to the second embodiment. Sincethe capacitance between the floating gates can be decreased, thestructure hardly suffers the memory cell threshold fluctuation caused bythe potential of adjacent floating gates, i.e., the so-called proximityeffect. As described above, the memory cell obtained according to thethird embodiment has the structure that hardly suffers the proximityeffect. This is also advantageous in further micropatterning memorycells.

Fourth Embodiment

The fourth embodiment is the third example when the first embodiment isapplied to actual manufacturing steps.

FIGS. 27, 29, 31, 33, 35, 37, 39, and 41 are plan views showing anexample of a semiconductor device manufacturing method according to thefourth embodiment of the present invention in the order of mainmanufacturing steps. FIGS. 28A, 28B, 30A, 30B, 32A, 32B, 34A, 34B, 34C,36A, 36B, 38A, 38B, 40A, 40B, 42A, and 42B are sectional views showingthe example of the semiconductor device manufacturing method accordingto the fourth embodiment of the present invention in the order of mainmanufacturing steps.

First, as shown in FIGS. 27, 28A, and 28B, shallow trenches ST areformed in a silicon substrate 4 and filled with insulating films 9, inthis embodiment, silicon oxide films 9, following the same procedure asexplained in the second embodiment until the step shown in FIGS. 12,13A, and 13B. In this embodiment, however, the thicknesses of insulatingfilms (CAP) 7 and silicon nitride films 7 are made larger than those inthe second and third embodiments.

Then, as shown in FIGS. 29, 30A, and 30B, the silicon nitride films 7are used as etching masks to dry-etch or wet-etch the silicon oxidefilms 9 and silicon oxide films 14. This embodiment dry-etches orwet-etches the silicon oxide films 9 and 14 to the middle of the sidesurfaces of the silicon nitride films 7. Consequently, the uppersurfaces of the silicon oxide films 9 and 14 lower to the middle of theside surfaces of the silicon nitride films 7.

As shown in FIGS. 31, 32A, and 32B, amorphous silicon, for example, isdeposited on the silicon nitride films 7 and silicon oxide films 9 and14 by using LP-CVD (Low Pressure CVD), thereby forming an amorphoussilicon film 15. Then, the silicon nitride films 7 are used as polishingstoppers to perform chemical-mechanical polishing (CMP) on the amorphoussilicon film 15. Subsequently, the silicon nitride films 7 are used asetching masks to dry-etch the amorphous silicon film 15, therebyrecessing it. Consequently, the amorphous silicon film 15 remains aroundthe silicon nitride films 7 remaining in the forms of pillars.

As shown in FIGS. 33, 34A, and 34B, boron ions (B⁺) 16 are implantedparallel to the word line direction and obliquely to the siliconsubstrate 4. Adjusting the implantation angle hides portions of theamorphous silicon film 15 behind the silicon nitride films 7. The boronions (B⁺) 16 are not implanted into these hidden portions. As a result,regions 15′ (boron-doped amorphous silicon films) into which the boronions (B⁺) 16 are selectively implanted are formed parallel to the wordline direction in the amorphous silicon film 15.

As shown in FIG. 34C, the implantation angle α of the boron ions (B⁺) 16is desirably larger than an angle β determined by the space width in theword line direction and the height of the silicon nitride film 7 abovethe upper surface of the amorphous silicon film 15. This is so in orderto form, in the amorphous silicon film 15, regions into which the boronions (B⁺) 16 are not implanted and the regions 15′ into which the boronions (B⁺) 16 are implanted.

As shown in FIGS. 35, 36A, and 36B, the silicon nitride films 7 are usedas etching masks to wet-etch the amorphous silicon film 15 by using,e.g., an alkaline etchant. Of the amorphous silicon film 15, the regionsof the boron-doped amorphous silicon films 15′ are not etched but remainbecause the alkali etching rate of these regions is lower than that ofthe rest.

As shown in FIGS. 37, 38A, and 38B, the silicon nitride films 7 andboron-doped amorphous silicon films 15′ are used as etching masks todry-etch the silicon oxide films 9. This embodiment dry-etches thesilicon oxide films 9 to the middle of the side surfaces ofphosphorus-doped polysilicon films 6. This lowers the upper surfaces ofthe silicon oxide films 9 to the middle of the side surfaces of thephosphorus-doped polysilicon films 6, thereby exposing the side surfacesof the phosphorus-doped polysilicon films 6.

As shown in FIGS. 39, 40A, and 40B, the silicon nitride films 7 andsilicon oxide films 9 are used as etching masks to dry-etch theboron-doped amorphous silicon films 15′, thereby removing them. Then,the silicon oxide films 9 and 14 are used as etching masks to wet-etchthe silicon nitride films 7, thereby removing them and exposing theupper surfaces of the phosphorus-doped polysilicon films 6.

As shown in FIGS. 41, 42A, and 42B, an interpoly insulator 10 isdeposited on the silicon oxide films 9 and 14 and phosphorus-dopedpolysilicon films 6. An example of the interpoly insulator 10 can be thesame as in the second embodiment, i.e., a silicon oxide film. An exampleof the formation method can also be the same as in the secondembodiment. A conductor 11 is then deposited on the silicon oxide film10. An example of the conductor 11 can be the same as in the secondembodiment, i.e., a phosphorus-doped polysilicon film. An example of theformation method can also be the same as in the second embodiment.Subsequently, the silicon oxide film 10 is used as a polishing stopperto perform chemical-mechanical polishing (CMP) on the phosphorus-dopedpolysilicon film 11, thereby burying the phosphorus-doped polysiliconfilm 11 in spaces between the patterns formed by alternately arrangingthe silicon oxide films 9 and 14. This forms word lines WL without usingany word line mask patterns, unlike in the second and third embodiments.

The above steps form a memory cell array of a stacked gate NAND flashmemory.

Similar to the first to third embodiments, the fourth embodiment alsoseparates the phosphorus-doped polysilicon film 6 as the material offloating gates along the word line direction before forming the shallowtrenches ST that taper the silicon oxide films 9. As in the first tothird embodiments, therefore, the phosphorus-doped polysilicon films 6do not remain in hidden portions formed by the taper.

Also, similar to the third embodiment, the fourth embodiment exposes theside surfaces of the conductor films 6 serving as floating gates bylowering the upper surfaces of the insulating films (STI) 9 to themiddle of the side surfaces of the conductor films 6. As in the thirdembodiment, therefore, it is possible to make the capacitance betweenthe floating gate and control gate (word line) larger than that in thesecond embodiment. In addition, similar to the third embodiment, thefloating gates 6 in the word line direction sandwich the conductor films11. This makes it possible to decrease the capacitance between floatinggates adjacent to each other along the word line direction, compared tothe second embodiment.

Furthermore, the fourth embodiment forms word lines in self-alignmentwith the conductor films 6 serving as floating gates formed before theformation of the shallow trenches ST. This eliminates capacitancevariations caused by misalignment of lithography between the floatinggates and control gates (word lines), compared to the first to thirdembodiments. The manufacturing cost can also be reduced compared to thefirst to third embodiments, because no lithography step of forming wordlines is necessary.

Fifth Embodiment

The fifth embodiment is an example of a semiconductor integrated circuitdevice having a nonvolatile semiconductor memory manufactured by themanufacturing methods according to the above embodiments.

FIGS. 48 and 49 are sectional views showing an example of thesemiconductor integrated circuit device according to the fifthembodiment of the present invention. FIG. 48 is a sectional view takenalong the word line direction, and corresponds to the section shown in,e.g., FIG. 21A. FIG. 49 is a sectional view taken along the bit linedirection, and corresponds to the section shown in, e.g., FIG. 21B. Notethat FIGS. 48 and 49 illustrate sections when bit lines are formed.

FIGS. 50, 51, and 52 are perspective views showing the example of thesemiconductor integrated circuit device according to the fifthembodiment of the present invention. FIG. 50 shows the state in whichinsulating films 7 as cap layers are removed from the upper surfaces ofconductor films 6 as floating gates, and corresponds to a perspectiveview showing the step illustrated in, e.g., FIGS. 14, 15A, and 15B. FIG.51 is a perspective view when an inter-gate insulating film (interpolyinsulator) 10 is formed on the structure shown in FIG. 50. FIG. 52 is aperspective view when word lines are formed.

As shown in FIGS. 48 to 52, the surface of a semiconductor substrate 4has element isolation regions 9 extending in a first direction, andelement regions AA defined by the element isolation regions 9. In thisembodiment, the semiconductor substrate 4 is a p-type silicon substrate(or a p-type well). Also, in this embodiment, the element isolationregions 9 are shallow trench isolations obtained by burying an insulatorin shallow trenches, and the first direction is the bit line direction.The element regions AA are portions where the sources, drains, andchannels of memory cell transistors and block selection transistors areformed. In this embodiment, the element regions AA extend in the firstdirection (bit line direction) along the element isolation regions. Gateinsulating films 5 are formed on the element regions AA. Since thisembodiment assumes a NAND flash memory, the gate insulating film 5 is atunnel insulating film, and an example is a silicon oxide film. Chargestorage layers 6 are formed on the gate insulating films 5. Since thisembodiment assumes a stacked gate memory cell transistor, the chargestorage layer 6 is a floating gate. Side surfaces 21 and 22 of thecharge storage layer 6, which extend along the element isolation region9 are in contact with it. Insulating films 14 that separate the chargestorage layers 6 along the first direction (bit line direction) areformed above the element regions AA. In this embodiment, the insulatingfilms 14 are silicon oxide films, and formed on the gate insulatingfilms 5 formed on the element regions AA. Note that the gate insulatingfilms 5 below the insulating films 14 may also be omitted. Each chargestorage layer 6 (e.g., FG in the drawing) has two side surfaces 23 and24 that intersect the side surfaces extending along the elementisolation region 9. One insulating film 14 (14L) is in contact with theside surface 23, and another insulating film 14 (14R) is in contact withthe side surface 24.

In this embodiment, the position of an upper surface 25 of the chargestorage layer 6 is lower than that of an upper surface 26 of theinsulating film 14 and that of an upper surface 27 of the elementisolation region 9.

An inter-gate insulating film (interpoly insulator) 10 is formed on theinsulating films 14, charge storage layers 6, and element isolationregions 9. In this embodiment, the inter-gate insulating film 10 is madeof silicon oxide, and formed on the entire surface of the structureshown in FIG. 50.

Control gates (word lines) 11 are formed on the inter-gate insulatingfilm 10. In this embodiment, the control gates run in a second direction(the word line direction) perpendicular to the first direction (bit linedirection). The control gates 11 oppose the charge storage layers 6 viathe inter-gate insulating film 10. Although insulating films 12 as caplayers are formed on the control gates 11 in this embodiment, theinsulating films 12 may also be omitted. An interlayer dielectric film28 is formed on the inter-gate insulating films 10 and control gates 11(in this embodiment, the insulating films 12). Bit lines BL are formedon the interlayer dielectric film 28. Also, in the element regions AAbelow the insulting films 14, diffusion layers 29 having a conductivitytype (in this embodiment, an n-type) opposite to that of thesemiconductor substrate 4 are formed. The diffusion layers 29 functionas the source/drain regions of memory cell transistors. Note that theformation step of the diffusion layers 29 is omitted in the first tofourth embodiments. In the second embodiment, for example, after theconductor film 6 is patterned in the step shown in FIGS. 4, 5A, and 5B,the diffusion layers 29 can be formed by ion-implanting an n-typeimpurity into the substrate 4 by using the insulating films 7 as masks.

FIGS. 53A to 53C are views for explaining the advantage obtained fromthe semiconductor integrated circuit device according to the fifthembodiment. FIGS. 54A to 54C are views showing a semiconductorintegrated circuit device according to a reference example of the fifthembodiment.

First, the problem of the present NAND flash memories will be explainedbelow by using the reference example.

FIGS. 54A to 54C illustrate the sections in the bit line direction ofmemory cell transistors of NAND flash memories.

The degree of micropatterning of NAND flash memories is increasingyearly to meet demands for increasing the storage capacity. Especiallyin the section along the bit line direction, the gate length of memorycell transistors along the bit line direction is more and moredecreased. This is so in order to shorten the array of memory celltransistors in the bit line direction by decreasing the gate length. Inaccordance with this tendency, the sectional shape of the control gate(word line) 11 is vertically elongate in order to suppress the increasein resistance value of the control gate 11. That is, the sectional shapeof a stacked gate structure obtained by stacking the charge storagelayers (floating gates) 6 and control gates (word lines) 11 isvertically elongate. FIGS. 54A to 54C illustrate this tendency.

The aspect ratio is an index representing the sectional shape of astacked gate structure. The aspect ratio in this specification is(height H/gate length L). FIG. 54A shows a memory cell transistor havinga stacked gate structure with an aspect ratio of 3/2=1.5. FIG. 54B showsa memory cell transistor having a stacked gate structure with an aspectratio of 3/1=3. FIG. 54C shows a memory cell transistor having a stackedgate structure with an aspect ratio of 3/0.5=6. As the aspect ratiorises, the stacked gate structure is vertically elongate. The problem ofthe vertically long stacked gate structure is the difficulty ofprocessing of the stacked gate structure. For example, in the verticallylong stacked gate structure, a photoresist serving as an etching maskeasily falls during etching.

By contrast, the fifth embodiment does not process the control gates 11and charge storage layers 6 at once, but processes the control gates 11after processing the charge storage layers 6. In addition, afterprocessing the charge storage layers 6, the fifth embodiment forms theelement isolation regions 9 along the side surfaces 21 and 22 of thecharge storage layers 6, and forms the insulating films 14 along theside surfaces 23 and 24 of the charge storage layers 6. As shown inFIGS. 53A to 53C, therefore, even if the aspect ratio of the stackedgate structure is high, actual processing need only be performed up tothe element isolation regions 9 and insulting films 14, or up to theinter-gate insulating film 10 formed on the element isolation regions 9and insulating films 14. That is, the structure to be actually processedhas a low aspect ratio. Similar to FIG. 54A, FIG. 53A shows a memorycell transistor having a stacked gate structure with an aspect ratio of3/2=1.5. However, the aspect ratio (height H′) of the structure to beactually processed is less than 1.5. Assume, for example, that theheight H′ is ⅓ the height H, the aspect ratio is 1/2=0.5. Likewise, FIG.53B shows a memory cell transistor having a stacked gate structure withan aspect ratio of 3/1=3, similar to FIG. 54B. Assume that the height H′is ⅓ the height H, the aspect ratio is 1/1=1. Similar to FIG. 54C, FIG.53C shows a memory cell transistor having a stacked gate structure withan aspect ratio of 3/0.5=6. Assume that the height H′ is ⅓ the height H,the aspect ratio is 1/0.5=2.

As described above, the fifth embodiment processes the control gates 11after processing the charge storage layers 6. In addition, the fifthembodiment forms the element isolation regions 9 along the side surfaces21 and 22 of the charge storage layers 6, and forms the insulating films14 along the side surfaces of the charge storage layers 6. Consequently,it is possible to obtain the advantage that the aspect ratio of theportion to be processed can be lowered, and this facilitates processingof the stacked gate structure.

In addition, the fifth embodiment leaves the inter-gate insulating film10 behind on the insulating films 14 even after forming the controlgates 11. This structure makes it possible to obtain the advantage thatwhen a low-resistance metal is used as the control gates 11 in order todecrease the resistance value of the control gates 11, diffusion of thismetal to the gate insulating films (in this embodiment, the tunnelinsulating films) 5 can be prevented.

Examples of the low-resistance metal are cobalt (Co), nickel (Ni),titanium (Ti), Co silicide, Ni silicide, Ti silicide, tungsten (W),aluminum (Al), and copper (Cu).

The structure of the fifth embodiment is advantageous when any of thesemetals is used as the control gates 11.

Sixth Embodiment

Similar to the fifth embodiment, the sixth embodiment is an example of asemiconductor integrated circuit device.

FIGS. 55 and 56 are sectional views showing the example of thesemiconductor integrated circuit device according to the sixthembodiment of the present invention. FIG. 55 is a sectional view takenalong the word line direction, and corresponds to the section shown in,e.g., FIG. 26A. FIG. 56 is a sectional view taken along the bit linedirection, and corresponds to the section shown in, e.g., FIG. 26B. Notethat FIGS. 55 and 56 illustrate the sections when bit lines are formed.

FIGS. 57, 58, and 59 are perspective views showing the example of thesemiconductor integrated circuit device according to the sixthembodiment of the present invention. FIG. 57 shows the state in whichinsulating films 7 as cap layers are removed from the upper surfaces ofconductor layers 6 as floating gates, and corresponds to a perspectiveview showing the step illustrated in, e.g., FIGS. 23A and 23B. FIG. 58is a perspective view when an inter-gate insulating film (interpolyinsulator) 10 is formed on the structure shown in FIG. 57. FIG. 59 is aperspective view when word lines are formed.

The sixth embodiment differs from the fifth embodiment in that theposition of an upper surface 25 of the charge storage layer 6 is higherthan that of an upper surface 26 of an insulating film 14 as shown inFIG. 56, and higher than that of an upper surface 27 of an elementisolation region 9 as shown in FIG. 55. The rest is the same as in thefifth embodiment, so an explanation thereof will be omitted.

As in the fifth embodiment, the sixth embodiment also processes controlgates 11 after processing the charge storage layers 6. In addition,after processing the charge storage layers 6, the sixth embodiment formsthe element isolation regions 9 along side surfaces 21 and 22 of thecharge storage layers 6, and forms the insulating films 14 along sidesurfaces 23 and 24 of the charge storage layers 6. Accordingly, thesixth embodiment can also lower the aspect ratio of the portion to beprocessed. This makes it possible to obtain the advantage that thestacked gate structure is readily processed.

Furthermore, similar to the fifth embodiment, the sixth embodiment alsoleaves the inter-gate insulating film 10 behind on the insulating films14 after forming the control gates 11. When a low-resistance metal isused as the control gates 11, therefore, it is possible to preventdiffusion of this metal to gate insulating films (in this embodiment,the tunnel insulating films) 5.

The structure of the sixth embodiment is particularly advantageous whenany of cobalt (Co), nickel (Ni), titanium (Ti), Co silicide, Nisilicide, Ti silicide, tungsten (W), aluminum (Al), and copper (Cu) isused as the control gates 11.

Seventh Embodiment

Similar to the fifth and sixth embodiments, the seventh embodiment is anexample of a semiconductor integrated circuit device.

FIGS. 60 and 61 are sectional views showing the example of thesemiconductor integrated circuit device according to the seventhembodiment of the present invention. FIG. 60 is a sectional view takenalong the word line direction, and corresponds to the section shown in,e.g., FIG. 42A. FIG. 61 is a sectional view taken along the bit linedirection, and corresponds to the section shown in, e.g., FIG. 42B. Notethat FIGS. 60 and 61 illustrate the sections when bit lines are formed.

FIGS. 62, 63, and 64 are perspective views showing the example of thesemiconductor integrated circuit device according to the seventhembodiment of the present invention. FIG. 62 shows the state in whichinsulating films 7 as cap layers are removed from the upper surfaces ofconductor films 6 as floating gates, and corresponds to a perspectiveview showing the step illustrated in, e.g., FIGS. 39, 40A, and 40B. FIG.63 is a perspective view when an inter-gate insulating film (interpolyinsulator) 10 is formed on the structure shown in FIG. 62. FIG. 64 is aperspective view when word lines are formed.

The seventh embodiment differs from the fifth embodiment in that theposition of an upper surface 25 of the charge storage layer 6 is lowerthan that of an upper surface 26 of an insulating film 14 as shown inFIG. 61, and higher than that of an upper surface 27 of an elementisolation region 9 below a control gate 11 as shown in FIG. 60.

The seventh embodiment forms the control gates 11 by burying them intrenches 32 formed in the insulating films 14 and element isolationregions 9 shown in FIGS. 62 and 63, and hence obviates the need for alithography step of forming the control gates 11. This is the same asexplained in the fourth embodiment.

In addition, in this embodiment as well shown in FIGS. 62 to 64, theposition of upper surfaces 30 of the inter-gate insulating film 10 onthe insulating films 14 and element isolation regions 9 is the same asthat of upper surfaces 31 of the control gates 11.

This arrangement can achieve the following advantage.

FIGS. 65A to 65C are views for explaining the advantage obtained fromthe semiconductor integrated circuit device according to the seventhembodiment. FIGS. 66A to 66C are views showing a semiconductorintegrated circuit device according to a reference example of theseventh embodiment.

First, the problem of the present NAND flash memories will be explainedby using the reference example.

As shown in FIGS. 66A to 66C, when connecting an electricalinterconnection to the control gate 11, the contact hole 32 and aconductive contact (plug) 33 are formed in an interlayer dielectric film28′. In this reference example, the interlayer dielectric film 28′ isformed on the element isolation region 9.

When the interlayer dielectric film 28′ and element isolation region 9are made of the same insulator, e.g., silicon oxide, etching sometimesreaches the element isolation region 9 from the interlayer dielectricfilm 28′ when forming the contact hole 32 shown in FIG. 66B. This is sobecause etching largely varies depending on the processing conditions.The amount of etching to the element isolation region 9 readily changesdepending on the position in a chip or the position on a wafer, orreadily changes from one wafer to another. This varies the contact areabetween the control gate 11 and conductive contact 33, and also variesthe depth of the contact hole 32, i.e., the size of the conductivecontact 33. These variations have influence on the electricalcharacteristics of the control gate 11. That is, these variations changethe resistance value obtained via the conductive contact 33 and aninterconnection 34 from a circuit that controls the control gate 11 tothe control gate 11, and change the interconnection capacitance. In thisexample, the control gate 11 is a word line. If the resistance value andinterconnection capacitance change, therefore, the CR time constant ofthe word line varies.

The variation in CR time constant of the word line makes it difficult toincrease the speed of, e.g., read and write operations. This is sobecause, e.g., the times of application of a read voltage and writevoltage to word lines must fit a word line having the worst electricalcharacteristics.

Also, the number of values of multilevel data that a memory cell storesis recently increasing to 3, 4, 8, 16, 32, . . . . As the number ofvalues of multilevel data thus increases, a read voltage andverification read voltage to be applied to a word line are set morefinely. For example, the number of setting levels of each of the readvoltage and verification read voltage is “7” if the number of values is8, “15” if the number of values is 16, and “31” if the number of valuesis 32. It is difficult to set, e.g., “7×2=14”, “15×2=30”, or “31×2=62”voltages in a certain predetermined voltage range unless the variationin CR time constant of the word line is small.

Note that in this specification, a multilevel nonvolatile semiconductormemory means a memory that stores data having 3 values (1.5 bits) ormore in one memory cell transistor.

By contrast, as shown in the sectional views of FIGS. 65A to 65C, theseventh embodiment forms the inter-gate insulating film 10 on theelement isolation region 9, and forms the interlayer dielectric film 28′on the control gate 11 and inter-gate insulating film 10. The interlayerdielectric film 28′ has the contact hole 32 that exposes the uppersurface 31 of the control gate 11 and the upper surface 30 of theinter-gate insulating film 10. In addition, the interlayer dielectricfilm 28′ is made of an insulator different from the inter-gateinsulating film 10.

This arrangement allows the inter-gate insulating film 10 to be used asan etching stopper when forming the contact hole 32 by etching theinterlayer dielectric film 28′. The etching stops at the inter-gateinsulating film 10 and hence does not reach the element isolation region9. Consequently, as shown in FIG. 65B, the area of the control gate 11exposed from the contact hole 32 has a predetermined size. When theconductive contact 33 is formed in the contact hole 32 like this, theresistance value obtained via the conductive contact 33 and aninterconnection 34 from a circuit that controls the control gate 11 tothe control gate 11 hardly changes, and the interconnection capacitancealso rarely changes, when compared to the case that there is nointer-gate insulating film 10.

In this embodiment, the control gate 11 is a word line. In thisembodiment, therefore, the CR time constant of the word line hardlyvaries. Since the CR time constant of the word line thus rarely varies,this embodiment is advantageous to raise the operating speed of anonvolatile semiconductor memory, e.g., a NAND flash memory. Inaddition, since the CR time constant of the word line hardly varies,many voltages can be easily set for the word line. Accordingly, thisembodiment is also useful for a multilevel NAND flash memory.

FIG. 67 shows an application example of the conductive contact 33 shownin FIG. 65C.

As shown in FIG. 67, the conductive contacts 33 shown in FIG. 65C can beused as conductive contacts that connect the interconnections 34 fromthe outputs of an address decoder, in this embodiment, a row decoder tothe control gates 11, in this embodiment, word lines WL arranged in thememory cell array.

Note that similar to the fifth and sixth embodiments, the seventhembodiment also leaves the inter-gate insulating film 10 behind on theinsulating films 14 after forming the control gates 11. When alow-resistance metal is used as the control gates 11, therefore, it ispossible to prevent diffusion of this metal to gate insulating films (inthis embodiment, tunnel insulating films) 5.

The structure of the seventh embodiment is particularly advantageouswhen any of cobalt (Co), nickel (Ni), titanium (Ti), Co silicide, Nisilicide, Ti silicide, tungsten (W), aluminum (Al), and copper (Cu) isused as the control gates 11.

Eighth Embodiment

The eighth embodiment is a modification of the sixth embodiment.

FIGS. 68 and 69 are sectional views showing an example of asemiconductor integrated circuit device according to the eighthembodiment of the present invention. FIG. 68 is a sectional view takenalong the word line direction, and corresponds to the section shown in,e.g., FIG. 26A. FIG. 69 is a sectional view taken along the bit linedirection, and corresponds to the section shown in, e.g., FIG. 26B. Notethat FIGS. 68 and 69 illustrate the sections when bit lines are formed.

FIGS. 70, 71, and 72 are perspective views showing the example of thesemiconductor integrated circuit device according to the eighthembodiment of the present invention. FIG. 70 shows the state in whichinsulating films 7 as cap layers are removed from the upper surfaces ofconductor films 6 as floating gates, and corresponds to a perspectiveview showing the step illustrated in, e.g., FIGS. 23A and 23B. FIG. 71is a perspective view when an inter-gate insulating film (interpolyinsulator) 10 is formed on the structure shown in FIG. 70. FIG. 72 is aperspective view when word lines are formed.

The eighth embodiment differs from the sixth embodiment in that a length(to be referred to as a floating gate length hereinafter) L_(FG) in afirst direction, in this embodiment, the bit line direction, of thecharge storage layer 6 is smaller than a length (to be referred to as acontrol gate length hereinafter) L_(CG) in the first direction, in thisembodiment, the bit line direction, of a control gate 11. This is shownin, e.g., FIG. 69.

One advantage of the eighth embodiment is that a coupling capacitance C1between the charge storage layer 6 and control gate 11 can be madelarger than a coupling capacitance C2 between a channel below the chargestorage layer 6 and the charge storage layer 6, when compared to thesixth embodiment. That is, a capacitance coupling ratio C1/C2 can beincreased.

As shown in FIGS. 70 and 71, for example, the eighth embodiment formsthe inter-gate insulating film 10 on an upper surface 25 of the chargestorage layer 6, on two side surfaces 21 and 22 along the firstdirection, in this embodiment, the bit line direction of the chargestorage layer 6, and on two side surfaces 23 and 24 along a seconddirection, in this embodiment, the word line direction of the chargestorage layer 6.

In addition, the control gate 11 opposes, via the inter-gate insulatingfilm 10, the upper surface 25 of the charge storage layer 6, the twoside surfaces 21 and 22 along the first direction (in this embodiment,the bit line direction) of the charge storage layer 6, and the two sidesurfaces 23 and 24 along the second direction (in this embodiment, theword line direction) of the charge storage layer 6. This makes itpossible to increase the coupling capacitance C1 between the chargestorage layer 6 and control gate 11, compared to the sixth embodiment inwhich the control gate 11 opposes the upper surface 25 and side surfaces21 and 22 of the charge storage layer 6 via the inter-gate insulatingfilm 10. When the capacitance coupling ratio C1/C2 is high, electriccharge is readily injected into the charge storage layer 6 during datawrite. This is advantageous in increasing the operating speed of thewrite operation.

When compared to the sixth embodiment, the eighth embodiment can alsoachieve three advantages 1 to 3 below:

(Advantage 1) The eighth embodiment is strong against mask misalignment.

(Advantage 2) The eighth embodiment hardly suffers the proximity effect.

(Advantage 3) The eighth embodiment easily raises the channel potential.

These three advantages will be explained below in order.

(Advantage 1)

FIGS. 73A and 73B are views for explaining advantage 1 obtained from thesemiconductor integrated circuit device according to the eighthembodiment.

FIGS. 74A and 74B are views showing a reference example.

The reference example will be explained first.

The reference example shown in FIGS. 74A and 74B is the case that thecontrol gate length L_(CG) and floating gate length L_(FG) are equal.

If mask misalignment occurs in the bit line direction in this case, asshown in FIG. 74B, the control gate 11 opposes one of the sides surfaces23 and 24 of the charge storage layer 6 via the inter-gate insulatingfilm 10. The difference between the states shown in FIGS. 74A and 74B isthat the control gate 11 opposes only the upper surface 25 of the chargestorage layer 6 or opposes one of the side surfaces 23 and 24 and theupper surface 25 of the charge storage layer 6. This means that thestates shown in FIGS. 74A and 74B are different in capacitance couplingratio C1/C2. If the capacitance coupling ratios C1/C2 are different, thecapacitance coupling ratio C1/C2 changes, e.g., from one chip toanother. This increases, e.g., the variation in write characteristicsbetween the chips. This variation also makes it difficult to increasethe operating speed of the write operation. This is so because theapplication time of a write voltage and the number of applied pulses ofthe write voltage must fit a memory cell transistor having the worstwrite characteristics.

By contrast, in the eighth embodiment as shown in FIG. 73A, the controlgate 11 opposes the side surfaces 23 and 24 and upper surface 25 of thecharge storage layer 6 via the inter-gate insulating film 10. As shownin FIG. 73B, therefore, even if mask misalignment occurs in the bit linedirection, the capacitance coupling ratio C1/C2 remains unchangedbecause the control gate 11 opposes the side surfaces 23 and 24 andupper surface 25 of the charge storage layer 6 via the inter-gateinsulating film 10. This makes the eighth embodiment strong against maskmisalignment. For example, the variation in write characteristicsbetween chips hardly increases. This is advantageous in increasing theoperating speed of the write operation.

Note that as shown in FIG. 75, to achieve advantage 1 better, lettingL_(CG) be the length in the first direction (in this embodiment, the bitline direction) of the control gate 11, t_(IGI) be the thickness of theinter-gate insulating film 10 on the side surfaces 23 and 24 along thesecond direction (in this embodiment, the word line direction) of thecharge storage layer 6, and M_(A) be an alignment margin in the firstdirection when processing the control gate 11, the length L_(FG) in thefirst direction of the charge storage layer 6 is preferably set to havethe relationship indicated by L_(FG)<L_(CG)−2M_(A)−2t_(IGI).

It is still possible, without setting the above relationship, to obtainthe advantage that the variation in write characteristics between chipsdecreases. However, setting the above relationship further decreases thevariation in write characteristics between chips.

(Advantage 2)

FIG. 76 is a view for explaining advantage 2 obtained from thesemiconductor integrated circuit device according to the eighthembodiment. FIG. 77 is a view showing a reference example.

As shown in FIG. 76, a distance P_(FG-FG) between the charge storagelayers 6 in the eighth embodiment is larger than that in the referenceexample shown in FIG. 77. This achieves the following advantage.

The distance P_(FG-FG) between the charge storage layers 6 is decreasingas the degree of micropatterning of memory cell transistors of NANDflash memories increases. In addition, the number of values ofmultilevel storage information is increasing, and the threshold voltagedistribution width corresponding to the storage information isdecreasing accordingly. As these tendencies advance, phenomena that havehardly appeared in the past are beginning to emerge. An example is athreshold fluctuation caused by the potentials of the charge storagelayers 6 in adjacent memory cell transistors. This threshold fluctuationis called the proximity effect. The proximity effect fluctuates thethreshold value of a memory cell in which data is already written. Thismakes it difficult to decrease the threshold distribution width.

The proximity effect will be briefly explained below.

A nonvolatile semiconductor memory, e.g., a NAND flash memory writesdata page by page. That is, when completely writing data in one page,write to the next page begins. A page is generally set for each wordline. Data is written in order from a memory cell transistor (to bereferred to as a memory cell hereinafter) on the source side farthestfrom a bit line to a memory cell on the bit line side. For example, datais first written in a memory cell MC1 connected to a word line WL1 (FIG.78A), and then written in a memory cell MC2 connected to a word line WL2(FIG. 78B).

Assume that data “0” is to be written in the memory cell MC2. When data“0” is written, electrons e are injected into a charge storage layer FG2of the memory cell MC2, so the potential of the charge storage layer FG2drops. The charge storage layer FG2 is adjacent in the bit linedirection to the charge storage layer FG1 of the memory cell MC1 via aninsulator. The charge storage layer FG2 electrically couples with thecharge storage layer FG1 via a parasitic capacitance C_(ff). When theelectrons e are injected and the potential of the charge storage layerFG2 drops, the charge storage layer FG1 capacitively couples with thecharge storage layer FG2, and the potential of the charge storage layerFG1 drops. Data is already written in the memory cell MC1. The potentialdrop of the charge storage layer FG1 of the written memory cell MC1means that a threshold value Vth of the written memory cell MC1 haschanged. This is the proximity effect. FIG. 79A shows a thresholddistribution Dw of a memory cell before it suffers the proximity effect.FIG. 79B shows a threshold distribution Dw′ after the memory cell hassuffered the proximity effect.

As shown in FIGS. 79A and 79B, the proximity effect increases thethreshold distribution width Dw of the written memory cell to thedistribution width Dw′. This makes it difficult to control the thresholdvoltage distribution within a target range.

The proximity effect occurs not only in the binary memory shown in FIGS.79A and 79B, but also in a multilevel memory. The influence of theproximity effect is particularly large in a multilevel memory becausethe threshold voltage distribution width Dw of a multilevel memory mustbe smaller than that of a binary memory. For example, FIGS. 80A and 80Bshow the case that a quaternary memory has suffered the proximityeffect, and FIGS. 81A and 81B show the case that an octernary memory hassuffered the proximity effect. As shown in FIGS. 80A to 81B, as thenumber of values of storage information increases, the thresholddistribution width Dw decreases, and the margin for the proximity effectdecreases.

By contrast, in the eighth embodiment as shown in FIG. 76, the distanceP_(FG-FG) between the charge storage layers 6 increases compared to thereference example shown in FIG. 77, so the parasitic capacitance C_(ff)decreases. The decrease in parasitic capacitance C_(ff) decreases thethreshold fluctuation of a memory cell in which data is already written,when compared to the reference example shown in FIG. 77.

Accordingly, the eighth embodiment hardly suffers the proximity effect.

Furthermore, in this embodiment, the control gates 11 exist between thecharge storage layers 6. For example, reference numeral 40 denotes suchportions in FIG. 76. Since the potential of the control gate is fixedduring data write, the potential fluctuation of the charge storage layer6 is further suppressed.

The eighth embodiment rarely suffers the proximity effect from thisviewpoint as well.

The eighth embodiment as described above is useful as a multilevelnonvolatile semiconductor memory larger than a ternary memory. Examplesare a quaternary memory, octernary memory, and hexadecimal memory.

(Advantage 3)

FIG. 82 is a view for explaining advantage 3 obtained from thesemiconductor integrated circuit device according to the eighthembodiment. FIG. 83 is a view showing a reference example.

In the eighth embodiment as shown in FIG. 82, a distance D_(CG-SUB)between the control gate 11 and substrate 4 is shorter than that in thereference example shown in FIG. 83. This achieves the followingadvantage.

Before writing data in a memory cell transistor, a NAND flash memoryremoves electric charge, in this embodiment, electrons, from all thecharge storage layers 6 in a block in which the data is to be written,thereby erasing data. Assume that in this specification, the data erasedstate is “1” in a binary memory, “11” in a quaternary memory, and “111”in an octernary memory (FIGS. 79A, 80A, and 81A).

When writing data, electrons are injected or not injected in the chargestorage layer 6 from which electrons are emitted, thereby writing data“0” or “1”. When electrons are injected, data “1” changes to data “0”(data “0” write). When no electrons are injected, the charge storagelayer 6 maintains the erased state or, in a multilevel memory, maintainsthe preceding written state, so data “1” remains (data “1” write).

In data “0” write, the potential difference between the control gate 11and the channel of a selected memory cell transistor is increased. Forexample, a write voltage Vpgm is applied to the control gate 11 of theselected memory cell transistor, and the channel of the selected memorycell transistor is set at a low voltage, e.g., 0V.

In data “1” write, the potential difference between the control gate 11and the channel of a selected memory cell transistor is decreased. Forexample, the write voltage Vpgm is applied to the gate 11 of theselected memory cell transistor, and a voltage close to the voltage Vpgmis applied to the channel of the selected memory cell transistor. Amethod called a self-boost method is a technique that makes the channelvoltage close to the voltage Vpgm.

The self-boost method will be briefly explained below.

FIG. 84 is a sectional view taken along the bit line direction, whichshows one block of a NAND flash memory to which the present invention isapplied.

As shown in FIG. 84, one block of the NAND flash memory extends from asource-side block selection transistor STSn to a drain-side blockselection transistor STDn. In this embodiment, 32 memory cells MC1 toMC32 are connected in series between the source-side block selectiontransistor STSn and drain-side block selection transistor STDn.

Before writing data in the memory cells MC1 to MC32, electrons areemitted from the charge storage layers 6 of the memory cells MC1 to MC32to, e.g., the substrate 4. Data is written while electrons are thusemitted from the charge storage layers 6 of the memory cells MC1 toMC32.

FIG. 85 is an operation timing chart showing the self-boost writemethod.

As shown in FIG. 85, at time t1, a voltage is applied to a bit line BLin accordance with whether write data is “0” or “1”. In this embodiment,“0V” is applied to the bit line BL in data “0” write, and “a writesuppressing potential”, in this embodiment, “a power supply voltage Vdd”is applied in data “1” write.

Then, at time t2, while a gate SGSn of the source-side block selectiontransistor STSn is set at 0V, a voltage Vsg is applied to a gate SGDn ofthe drain-side block selection transistor STDn. This turns off thetransistor STSn and turns on the transistor STDn, and 0V or the voltageVdd is supplied to the channel of the selected block. FIG. 85 shows thisstate. Although the potential of word lines WL1 to WL32 is 0V, thememory cells MC1 to MC32 are in the erased state, and the thresholdvoltage is, e.g., less than 0V. Since this turns on the channels of thememory cells MC31 and MC32, therefore, 0V or Vdd is transferred up to,e.g., the memory cell MC1 closest to the source (state I).

At time t3, the voltage of SGDn is lowered from the voltage Vsg to avoltage Vsgd. The voltage Vsgd turns on the transistor STDn if thevoltage of the bit line BL is 0V, and turns off the transistor STDn ifthe voltage of the bit line BL is Vdd. Consequently, if the channelvoltage is Vdd, the channels electrically float.

At time t4, the voltage of a selected word line, in this embodiment, theword line WL1 is raised from 0V to the write voltage Vpgm, and thevoltage of unselected word lines, in this embodiment, the word lines WL2to WL32 are raised from 0V to an intermediate voltage Vpass. As shown inFIG. 87, if the channels are electrically floating, they capacitivelycouple with the word lines WL1 to WL32.

That is, when suppressing charge injection to the charge storage layers6, this embodiment electrically floats the channels produced in theelement regions below the charge storage layers 6, thereby capacitivelycoupling the channel potential to the potential of the control gates 11.As a consequence, the channel potential rises from Vdd to Vboost (stateII).

When Vboost is close to the write voltage Vpgm, the potential differencebetween the control gate 11 and charge storage layer 6 decreases. Thissuppresses injection of electrons into the charge storage layer 6.

In the eighth embodiment as shown in FIG. 82, the lower surface of thecontrol gate 11 opposes the source/drain diffusion layers 29 formed inthe element region below the insulating film 14 and having aconductivity type opposite to that of the semiconductor substrate 4, viaat least the insulating film 14 and inter-gate insulating film 10. Thismakes the distance D_(CG-SUB) between the control gate 11 and substrate4 shorter than that in the reference example shown in FIG. 83. When thedistance D_(CG-SUB) shortens, the channel capacitively couples with thecontrol gate 11 more easily. That is, since Vboost can be easily madeclose to the write voltage Vpgm, it is possible to more stronglysuppress injection of electrons into the charge storage layer 6. Thismakes it possible to prevent a write error of data “0” when writing data“1”.

Also, when maintaining a previously written threshold voltage in amultilevel memory, the change in threshold voltage can be suppressedmore strongly. This facilitates obtaining a narrow threshold voltagedistribution.

The eighth embodiment is useful as a multilevel nonvolatilesemiconductor memory larger than a ternary memory from this viewpoint aswell. Examples are a quaternary memory, octernary memory, andhexadecimal memory.

Furthermore, the above embodiments include the following aspects.

(1) A semiconductor device manufacturing method comprises steps offorming a first insulating film on a semiconductor substrate, forming afirst conductor film on the first insulating film, forming a secondinsulating film on the first conductor film, etching the secondinsulating film and first conductor film into a first line-and-spacepattern, etching the second insulating film, first conductor film, firstinsulating film, and semiconductor substrate by a second line-and-spacepattern perpendicular to the first line-and-space pattern, burying athird insulating film in the etched region, removing the secondinsulating film, depositing a fourth insulating film on the firstconductor film and third insulating film, depositing a second conductorfilm on the fourth insulating film, and etching the second conductorfilm into a third line-and-space pattern parallel to the firstline-and-space pattern.

(2) There is provided a semiconductor device manufacturing methodaccording to aspect (1), wherein before depositing the fourth insulatingfilm, the third insulating film buried in the etched region is etched tothe middle of the film thickness of the first conductor film.

(3) A semiconductor device manufacturing method comprises steps offorming a first insulating film on a semiconductor substrate, forming afirst conductor film on the first insulating film, forming a secondinsulating film on the first conductor film, etching the secondinsulating film and first conductor film into a first line-and-spacepattern, etching the second insulating film, first conductor film, firstinsulating film, and semiconductor substrate into a secondline-and-space pattern perpendicular to the first line-and-spacepattern, burying a third insulating film in the etched region, etchingthe third insulating film to the middle of the second insulating film,forming a film on the etched region, implanting an impurity into thefilm parallel to the first line-and-space pattern and obliquely to thesemiconductor substrate, etching a portion of the film into which theimpurity is not implanted, etching the third insulating film to themiddle of the film thickness of the first conductor film by using theremaining portion of the film and the second insulating film as masks,removing the remaining portion of the film and the second insulatingfilm, forming a fourth insulating film on the first conductor film andthird insulating film, depositing a second conductor film on the fourthinsulating film, and partially removing the second conductor film toform a buried interconnection made of the second conductor film.

(4) There is provided a semiconductor device manufacturing methodaccording to aspect (3), wherein the impurity implanted into the film isa material selected from the group consisting of boron ions and ionscontaining boron.

(5) There is provided a semiconductor device manufacturing methodaccording to aspect (3), wherein the angle of implantation of theimpurity is larger than an angle determined by the space width of thesecond line-and-space pattern and the height of the second insulatingfilm closer to the surface than the silicon film.

(6) A semiconductor integrated circuit device comprises a semiconductorsubstrate having, in a surface, an element isolation region extending ina first direction, and an element region defined by the elementisolation region, a gate insulating film formed on the element region, acharge storage layer formed on the gate insulating film, and having sidesurfaces extending along and in contact with the element isolationregion, a first insulating film formed above the element region, and incontact with one of two side surfaces perpendicular to the side surfacesof the charge storage layer which extend along the element isolationregion, a second insulating film formed above the element region, and incontact with the other one of the two side surfaces perpendicular to theside surfaces of the charge storage layer which extend along the elementisolation region, an inter-gate insulating film formed on the first andsecond insulating films, charge storage layer, and element isolationregion, and a control gate formed on the inter-gate insulating film,opposing the charge storage layer via the inter-gate insulating film,and extending in a second direction perpendicular to the firstdirection.

(7) There is provided a semiconductor integrated circuit deviceaccording to aspect (6), wherein the position of the upper surface ofthe charge storage layer is lower than the position of the upper surfaceof the first and second insulating films, and the position of the uppersurface of the element isolation region.

(8) There is provided a semiconductor integrated circuit deviceaccording to aspect (6), wherein the position of the upper surface ofthe charge storage layer is higher than the position of the uppersurface of the first and second insulating films, and the position ofthe upper surface of the element isolation region.

(9) There is provided a semiconductor integrated circuit deviceaccording to aspect (6), wherein the position of the upper surface ofthe charge storage layer is lower than the position of the upper surfaceof the first and second insulating films, and higher than the positionof the upper surface of the element isolation region below the controlgate.

(10) There is provided a semiconductor integrated circuit deviceaccording to aspect (9), wherein the position of the upper surface ofthe inter-gate insulating film on the first and second insulating filmsand element isolation region is the same as the position of the uppersurface of the control gate.

(11) A semiconductor integrated circuit device according to aspect (10)further comprises an interlayer dielectric film formed on the controlgate and inter-gate insulating film, having a contact hole that exposesthe upper surface of the control gate and the upper surface of theinter-gate insulating film, and made of an insulator different from theinter-gate insulating film, and a conductive contact formed in thecontact hole and electrically connected to the control gate.

(12) There is provided a semiconductor integrated circuit deviceaccording to aspect (11), which further comprises an address decodingcircuit, and in which the conductive contact connects the output of theaddress decoding circuit and the control gate.

(13) There is provided a semiconductor integrated circuit deviceaccording to aspect (8), wherein the length in the first direction ofthe charge storage layer is smaller than the length in the firstdirection of the control gate.

(14) There is provided a semiconductor integrated circuit deviceaccording to aspect (13), wherein letting L_(CG) be the length in thefirst direction of the control gate, t_(IGI) be the thickness of theinter-gate insulating film on the side surfaces along the seconddirection of the charge storage layer, and M_(A) be an alignment marginin the first direction when processing the control gate, a length L_(FG)in the first direction of the charge storage layer has a relationshipindicated by L_(FG)<L_(CG)−2M_(A)−2t_(IGI).

(15) There is provided a semiconductor integrated circuit deviceaccording to aspect (13) or (14), wherein the control gate opposes theupper surface of the charge storage layer, the two side surfaces alongthe first direction of the charge storage layer, and the two sidesurfaces along the second direction of the charge storage layer via theinter-gate insulating film.

(16) There is provided a semiconductor integrated circuit deviceaccording to any one of aspects (13) to (15), wherein the lower surfaceof the control gate opposes source/drain diffusion layers formed in theelement region below the first and second insulating films and having aconductivity type opposite to the conductivity type of the semiconductorsubstrate, via at least the first and second insulating films andinter-gate insulating film.

(17) There is provided a semiconductor integrated circuit deviceaccording to aspect (16), wherein when suppressing charge injection tothe charge storage layer, a channel produced in the element region belowthe charge storage layer is electrically floated, thereby capacitivelycoupling the potential of the channel with the potential of the controlgate.

(18) There is provided a semiconductor integrated circuit deviceaccording to any one of aspects (6) to (17), wherein the control gate ismade of a material selected from the group consisting of cobalt (Co),nickel (Ni), titanium (Ti), Co silicide, Ni silicide, Ti silicide,tungsten (W), aluminum (Al), and copper (Cu).

(19) There is provided a semiconductor integrated circuit deviceaccording to any one of aspects (6) to (18), wherein the semiconductorintegrated circuit device is a NAND flash memory.

(20) There is provided a semiconductor integrated circuit deviceaccording to any one of aspects (6) to (19), wherein the semiconductorintegrated circuit device is a multilevel nonvolatile semiconductormemory.

The embodiments of the present invention can provide a semiconductordevice manufacturing method capable of preventing a shortcircuit betweenadjacent conductor patterns, e.g., a shortcircuit between adjacentfloating gates.

Although several embodiments of the present invention have beenexplained above, the present invention is not limited to theseembodiments but can be variously modified when practiced withoutdeparting from the spirit and scope of the invention.

For example, each embodiment has taken a stacked gate NAND flash memoryas an example, but the present invention is not limited to this memory.That is, the present invention is applicable to any semiconductor devicehaving a portion in which conductor patterns that should notshortcircuit are arranged adjacent to each other.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1.-5. (canceled)
 6. A semiconductor integrated circuit devicecomprising: a semiconductor substrate having an element isolation regionextending in a first direction, and an element region defined by theelement isolation region; a gate insulating film formed on the elementregion; a charge storage layer formed on the gate insulating film, andhaving a first side surface and a second side surface along the firstdirection and a third side surface and a fourth side surface along asecond direction perpendicular to the first direction, the first sidesurface being in contact with the element isolation region; a firstinsulating film formed above the element region, and in contact with thethird side surface of the charge storage layer; a second insulating filmformed above the element region, and in contact with the fourth sidesurface of the charge storage layer; an inter-gate insulating filmformed on the first insulating film, the second insulating film, thecharge storage layer, and the element isolation region; and a controlgate formed on the inter-gate insulating film, opposing the chargestorage layer via the inter-gate insulating film, and extending in thesecond direction.
 7. The device according to claim 6, wherein a positionof an upper surface of the charge storage layer is lower than a positionof an upper surface of the first insulating film and the secondinsulating film, and a position of an upper surface of the elementisolation region.
 8. The device according to claim 6, wherein a positionof an upper surface of the charge storage layer is higher than aposition of an upper surface of the first insulating film and the secondinsulating film, and a position of an upper surface of the elementisolation region.
 9. The device according to claim 6, wherein a positionof an upper surface of the charge storage layer is lower than a positionof an upper surface of the first insulating film and the secondinsulating film, and higher than a position of an upper surface of theelement isolation region below the control gate.
 10. The deviceaccording to claim 9, wherein a position of an upper surface of theinter-gate insulating film on the first insulating film, the secondinsulating film, and the element isolation region is the same as aposition of an upper surface of the control gate.
 11. The deviceaccording to claim 10, further comprising: an interlayer dielectric filmformed on the control gate and the inter-gate insulating film, having acontact hole which exposes the upper surface of the control gate and theupper surface of the inter-gate insulating film, and made of aninsulator different from the inter-gate insulating film; and aconductive contact formed in the contact hole and electrically connectedto the control gate.
 12. The device according to claim 11, which furthercomprises an address decoding circuit, and in which the conductivecontact connects an output of the address decoding circuit and thecontrol gate.
 13. The device according to claim 8, wherein a length inthe first direction of the charge storage layer is smaller than a lengthin the first direction of the control gate.
 14. The device according toclaim 8, wherein letting L_(CG) be a length in the first direction ofthe control gate, t_(IGI) be a thickness of the inter-gate insulatingfilm on the third side surface and the fourth side surface along thesecond direction of the charge storage layer, and M_(A) be an alignmentmargin in the first direction when processing the control gate, a lengthL_(FG) in the first direction of the charge storage layer has arelationship indicated by L_(FG)<L_(CG)−2M_(A)−2t_(IGI).
 15. The deviceaccording to claim 13, wherein the control gate opposes the uppersurface, the first side surface, the second side surface, the third sidesurface, and the fourth side surface of the charge storage layer via theinter-gate insulating film.
 16. The device according to claim 13,wherein source/drain diffusion layers are formed in the element regionbelow the first insulating film and the second insulating film and havea conductivity type opposite to a conductivity type of the semiconductorsubstrate, and a lower surface of the control gate opposes thesource/drain diffusion layers via at least the first insulating film,the second insulating film, and the inter-gate insulating film.
 17. Thedevice according to claim 16, wherein when suppressing charge injectionto the charge storage layer, a channel produced in the element regionbelow the charge storage layer is electrically floated, a potential ofthe channel is capacitive coupled with a potential of the control gate.18. The device according to claim 6, wherein the control gate is made ofa material selected from the group consisting of cobalt, nickel,titanium, cobalt silicide, nickel silicide, titanium silicide, tungsten,aluminum, and copper.
 19. The device according to claim 6, wherein thesemiconductor integrated circuit device is a NAND flash memory.
 20. Thedevice according to claim 6, wherein the semiconductor integratedcircuit device is a multilevel nonvolatile semiconductor memory.